Strained silicon polymer transistors aired to compound’s single hand applause.

Abstract

Gene Fitzgerald of MIT (and Amberwave Inc) discussed the history of strained silicon. He explained that there are only four big IC products that are surfing the advances of Moore’s Law: FPGA, DSP, microprocessors, and memory. Making existing sized designs with faster transistors will have more impact than stuffing more transistors on the same chip size. Another problem is in layout of large ICs with the interconnections between transistors. Fitzgerald looks at future microsystems as wanting to combine three vastly different functions: the digital, fast analog, and the interface with E&M waves. The last two functions are the bottle neck for microsystems, since they are made of compound semiconductors which have not been obeying the same manufacturing history curves as silicon. He finds that by adding enough layers and enough Ge to some of these layers that all functions can be made on the same chip using existing manufacturing equipment. One such layering system has strained silicon on top, next a Si (80%) Ge(20%), graded SiGe layer to reduce lattice mismatch and a bottom Si substrate. Using variations of these strained layers gives electron mobility of 80% with another Ge rich layer which eventually increases hole mobility by 800%. The low temperature formation of some of these layers is currently being addressed. If one of the layers has Ge >70%, one could add opto sources to the chip. One could also lower voltages even further with increased Ge. In summary, he considered that there is room for 1000% performance improvements by making ‘designer’ strained wafers for existing foundries. This is a short news story only. Visit www.three-fives.com for the latest advanced semiconductor industry news.