A Novel Technique For 3-d Integration: Ge-seeded Laterally Crystallized TFTs

Abstract

With increasing chip size and complexity, interconnect delays are becoming limiting factors in increasing performance. 3-D device integration will result in a reduction in chip size and interconnect delay. We present a novel technique for achieving high-performance MOS devices for vertical integration. Poly-Ge is used as a seeding agent to laterally crystallize amorphous Si films into the channel of poly-TFTs, resulting in a substantial performance improvement through a simple, CMOS-compatible process. The technology is scaleable, and should enable near-single crystal performance in deep sub-micron devices. Introduction As chip complexity and size has increased, interconnect delays have become a bottleneck limiting further improvement in chip speed. The delays associated with long interconnect lines is approaching the delays associated with individual active elements within the chip. Therefore, the need exists for a means to reduce chip size and average interconnect length through vertical integration of active devices. Unfortunately, no viable techniques exist today which allow this integration to be achieved. Techniques such as SIMOX allow SOI devices to be built on a single layer, but cannot be extended for 3-D integration. Controlled seeding in amorphous Si and subsequent lateral crystallization is a promising technique for achieving vertical integration. Crystallization occurs through nucleation and subsequent grain growth. Seeding is used to enhance nucleation in specific regions. These regions thus nucleate first and act as starting points for the lateral growth of large single-crystal islands. This controlled grain growth is the key to obtaining single-grain electronic devices. Metal-induced crystallization has been previously described (1). Unfortunately, metallic seeding agents such as Ni, are not CMOS-compatible, and therefore have questionable applicability to 3-D integration. We present a novel seeding technique which is low thermal budget, low-cost, simple, and CMOS-compatible, and is therefore extremely promising for achieving 3-D integration. Germanium is used as a seeding agent to laterally crystallize amorphous Si films. This results in large-grain polysilicon having spatially-specified grains. It is therefore possible to fabricate high-performance TFTs with excellent control over the position of grain boundaries. We present results detailing the performance of TFTs fabricated using this technique. We discuss the extension of this technique to deep sub-micron MOS devices for 3-D integration, offering near-single crystal performance. Seeding and Crystallization Methodology Ge is an excellent seeding agent for the solid-phase crystallization of amorphous Si. It can be deposited by LPCVD, and can be deposited selectively using an oxide mask over the amorphous silicon film. Poly-Ge can be deposited at low temperatures (<400°). After Ge deposition, the Si film is crystallized at low temperature to inhibit nucleation within the film. Grains grow laterally from the seeding points due to the lower activation energy associated with the Ge-Si interface. By placing the seeding points in the source/drain regions of a TFT, it is possible to laterally crystallize into the channel. After crystallization, the Ge is removed using a standard H2SO4:H2O2 clean. Thus the seeding technique is fully CMOS-compatible. The crystallization is a low temperature process. The thermal budget involved can be tailored to meet the needs of individual applications and device dimensions. Device Fabrication Devices were fabricated on oxidized silicon wafers to test the potential for 3-D integration. 100nm amorphous Si was deposited by LPCVD at 500°C followed by 50nm sacrificial SiO2. Seeding holes were patterned in the SiO2 and Ge was deposited by LPCVD at 450°C using a GeH4 chemistry. The Ge deposited selectively on the exposed Si through the holes. Following the Ge deposition, the films were crystallized at 500°C. After crystallization, the Ge and SiO2 were stripped using H2SO4:H2O2 and HF respectively. Planar topgate TFTs were then fabricated, positioning the seeding points in the source/drain regions of the devices. 30nm thermally-grown SiO2 (grown at 1000°C) was used as a gate dielectric. For comparison, unseeded TFTs were also fabricated using an identical process. The seeding and fabrication process is shown in figure 1. a) Deposit amorphous channel film b) Deposit and pattern sacrificial oxide c) Deposit germanium selectively d) Crystallize at low temperature e) Strip LTO, Ge and build TFT LTO Substrate a-Si Germanium Lateral crystallization Self-nucleation Substrate Channel Gate Source Drain LTO Gate Oxide Figure 1: Process flow Results Electrical measurements performed on the TFTs show that the seeding technique results in a substantial improvement in performance over unseeded devices. For comparison, transfer characteristics for unseeded and seeded PMOS devices are shown in fig. 2, showing improvement in both mobility and sub-threshold performance. 1.E-12 1.E-11 1.E-10 1.E-09 1.E-08 1.E-07 1.E-06 1.E-05 1.E-04 1.E-03