3-D ICs: Motivation, performance analysis, technology and applications

Abstract

Interconnect delays, bandwidth and power consumption are increasingly dominating IC performance due to increases in chip size and reduction in the minimum feature size, in spite of new materials like Cu with low-k dielectric. Thereby severely limiting chip performance unless a paradigm shift from present interconnect architecture is introduced. One such promising technique is three-dimensional (3-D) ICs with multiple active Si layers and vertical interconnects. This paper presents a comprehensive review of 3-D ICs with multiple semiconductor layers. It is shown that significant improvement in performance and reduction in wire-limited chip area can be achieved with 3-D ICs if some long horizontal interconnects can be replaced by short vertical inter-layer interconnects. We also address the thermal concerns due to increased power density for 3-D circuits. Finally, an overview of some of the processing techniques which can be used to fabricate these circuits, is reviewed.