Prospects of High-Ge-Content Strained SiGe for Advanced FinFET Generations

Abstract

High mobility materials such as strained Si1-xGexor III-V are promising channel candidates for advanced FinFET generations. By incorporation of moderate Ge content (x~0.2-0.3) into the channel of FinFETs, we have demonstrated pMOSFETs with superior extrinsic and intrinsic electrical characteristics suitable for 10nm technology generations and beyond [1]. To further boost pMOS FinFET performance, High-Ge-Content (HGC) SiGe FETs have recently drawn significant attention due to their enhanced transport and reliability properties and compatibility with bulk or SOI substrates [2, 3]. In addition, compared to strained pure germanium, they can offer reduced off-state tunneling leakage due to their relatively larger bandgap [4]. It has been observed that with high-Ge content around x~0.7, superior hole mobility values are achievable for planar biaxial strained SiGe on relaxed buffer layers and the mobility sensitivity to the strain level from underlying relaxed buffer is small when the buffer Ge content is above 30% [5]. Thus, HGC SiGe is an attractive pFET candidate especially when considered as a counterpart for nFET with s-Si FinFET technology [6], where higher Ge content is indeed required to compensate the built-in tension of s-Si. Utilization of HGC SiGe in a FinFET architecture by direct epitaxial growth is quite challenging due to very low (sub-10nm) epitaxial critical thickness constraints, resulting in high levels of defectivity which may be detrimental to the device functionality. In advanced FinFET technologies, relatively tall fins in tight pitches are required to increase the current per foot print and this may be quite challenging for high-Ge content strained SiGe FinFETs. Alternate approaches such as enhanced 3D Ge condensation [3] may be considered to mitigate the aforementioned issue. On the other hand, gate stack and interface passivation of SiGe with mid to high Ge range is more challenging than pure Si or pure Ge channel MOSFETs. While traditionally Si cap has been used to passivate the SiGe MOSFETs, this approach may not be optimal for scaled nodes where scaled EOT is required for electrostatics integrity of the transistors. Most devices fabricated using a Si-cap-free approach exhibit high levels of interface trap densities leading to mobility degradation and increased sub-threshold leakage. Moreover, enhance trap assisted tunneling can happen in the off state for high-Ge content SiGe due to its lower bandgap. In this talk, we review IBM's recent research activities on HGC SiGe FinFETs with Ge content over 50%. In particular, gate stack, passivation and EOT scaling are major factors in achieving high quality devices based on HGC SiGe. We present our results based on a Si-cap-free surface passivation combined with aggressive EOT scaling down to sub-7Å to achieve acceptable sub-threshold swings for both gate first and replacement high-K/metal gate FinFET integration flows. The width dependence of hole mobility for various device sizes from very wide (planar) to ultra-narrow (scaled FinFETs) would be presented and discussed in detail. In addition, various short channel device aspects such as impact of S/D junction process on performance and electrostatics, off-state leakage current, transconductance and current drive would be discussed. We conclude that high-Ge content SiGe FinFETs are suitable candidates for advanced high-performance logic FinFET applications, especially at low operating voltages (VDD), while their suitability for low or ultra-low power applications is questionable.