(Invited) Thin Epitaxial Single-Crystal Si on Sige Followed By in-Situ Deposition of High-k Dielectrics – Novel Gate Stacks for Achieving Extremely Low Dit and Highly Reliable SiGe MOS

Abstract

Silicon-germanium (SiGe) is replacing silicon (Si) as the channel layer for the p-type metal-oxide-semiconductor (pMOS) in the aggressively scaled complementary MOS (CMOS) technology. Many research efforts involving SiGe gate stacks have resulted in the attainment of low interfacial trap densities (Dits). Si-passivated SiGe gate stacks are the most promising method to achieve both low Dit and high device reliability. However, regardless of the growth methods, most publications reported the pileup of Ge atoms on top of the grown Si even after extensive treatments. The subsequent process in forming gate stacks, including oxidation, inevitably caused the segregated Ge to form GeOx, leading to degradation of the interfacial quality of the gate stacks.We have used molecular beam epitaxy (MBE) to grow thin single-crystal Si of 0.79nm thickness (six MLs) epitaxially on epi-Si1-xGex(001) under ultra-high vacuum (UHV). Different from its counterpart of chemical vapor deposition (CVD), MBE enables epi-Si growth on Ge at growth temperatures below 300 °C. The measurements using reflection high-energy electron diffraction (RHEED), high-resolution synchrotron radiation X-ray diffraction (HR-XRD), and the scanning transmission electron microscopy with high-angle annular-dark-field (STEM-HAADF) have revealed high crystallinity of the epi-Si, the Si1-xGex layers and abrupt interfaces of the high-k/epi-Si/Si1-xGex layers. Moreover, our unique capability of epi growth/analysis enabled the study of the electronic surface structures of epi-Si/epi-Ge using in-situ high-resolution synchrotron radiation photoemission spectroscopy (SRPES) via a portable sample transfer station under UHV. We have used SRPES to demonstrate that the as-grown Si1−xGex(001)-2×1 surfaces with Ge content ranging from 0.1 to 0.9 are all terminated with buckled Ge–Ge dimers, and the surface electronic structure is similar to that of epi-Ge(001)-2×1. The direct deposition of epi-Si on as-grown SiGe removed the top buckled Ge-Ge dimers, which diffused into the epi-Si and some segregated to the top of the Si. As a result, the topmost layer beneath the epi-Si was 1 ML of Ge, and the interfaces of high-k/epi-Si/Si1−xGex are similar to those of the high-k/epi-Si/Ge. Again, the hetero-interfaces of our gate dielectrics are different from those grown using CVD.The well-controlled interfaces have enabled the achievement of low interfacial trap densities (Dit) of (3 - 6) × 1011 eV-1cm-2 in these high-k/epi-Si/Si1-xGex samples. The minimum Dit values remained at 3 × 1011 eV-1cm-2 regardless of the Ge content, demonstrating the effective passivation of the low-temperature deposited epi-Si. The limited Ge segregation during the low-temperature growth of epi-Si may attribute to the attainment of the low Dit values. We have benchmarked the minimum Dit (Dit, min) of our work with other state-of-the-art SiGe gate stacks. The Dit,min values from the other efforts increased with increasing Ge content, which may be caused by the GeOx formation that was difficult to control in the high-Ge-content (HGC) Si1-xGex.The effective charge sheet densities for the Si1-xGex gate stacks were extracted via examination of capacitance-voltage (C-V) hysteresis with decreasing stress voltage in the accumulation region of the MOS capacitors. We have attained very high acceleration factors of 8-12, indicating high reliability of the HfO2/epi-Si/Si1-xGex pMOS gate stacks.Furthermore, we have used a scavenging method, consisting of a cyclic process of an O2 exposure followed by a UHV annealing, to eliminate the segregated and diffused Ge in epi-Si before high-k deposition. Upon O2 exposure at room temperature, both the Si and Ge surface atoms are simultaneously oxidized to give rise to four Si charge states and Ge suboxides, respectively. The subsequent in-situ annealing at 500 °C under UHV moved the oxygen atom in the Ge suboxides to bond with the nearby Si atom. The annealing also caused the diffused Ge inside the epi-Si to segregate to the surface. The processes of O2 exposure followed by annealing were repeated three times resulting in an oxidized Si/Ge surface having only the four Si oxidized states without GeOx, but with a minimal amount of segregated Ge.