SRAM voltage and current sense amplifiers in sub-32nm double-gate CMOS insensitive to process variations and transistor mismatch

Piotr Nasalski,Andrei Vladimirescu,Bastien Giraud,Adam Makosiej,Amara Amara

doi:10.1109/iscas.2009.5118476

SRAM voltage and current sense amplifiers in sub-32nm double-gate CMOS insensitive to process variations and transistor mismatch

Piotr Nasalski, Andrei Vladimirescu + Show 3 more

https://doi.org/10.1109/iscas.2009.5118476

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Publication Date: May 1, 2009

Citations: 16

Affiliation: University of Łódź, Lodz University of Technology, University of California, Berkeley, Institut Supérieur d'Électronique de Paris

#Current Sense Amplifiers #Voltage Sense Amplifiers + Show 8 more

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Abstract

This paper presents a comparative study of two novel sub-32 nm current (CSA) and voltage (VSA) sense amplifiers in fully depleted (FD) double-gate (DG) silicon-on-insulator (SOI) technology with planar independent self-aligned gates. The proposed sense amplifiers (SA) need 40% to 4 times less power, achieve a 10-15% increase in speed and have a 2.5 to 5 times larger tolerance to V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> and L mismatch compared to published DG SAs. Both architectures take advantage of the back gate in order to improve circuit properties. The new CSA is 12% faster and reduces power consumption 3.3 times compared to the new VSA, with the latter having a significant advantage in size.

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