Double-Gate Sub-32nm CMOS SRAM current and voltage sense amplifiers, insensitive to process variations and transistor mismatch

Adam Makosiej,Amara Amara,Andrei Vladimirescu,Bastien Giraud,Piotr Nasalski

doi:10.1109/soi.2008.4656295

Double-Gate Sub-32nm CMOS SRAM current and voltage sense amplifiers, insensitive to process variations and transistor mismatch

Adam Makosiej, Amara Amara + Show 3 more

https://doi.org/10.1109/soi.2008.4656295

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Publication Date: Oct 1, 2008

Citations: 1

Affiliation: University of Łódź, Lodz University of Technology, Institut Supérieur d'Électronique de Paris, University of California, Berkeley

#Voltage Sense Amplifiers #Sense Amplifiers + Show 8 more

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Abstract

This paper describes two novel sub-32 nm current (CSA) and voltage (VSA) sense amplifiers in fully depleted (FD) double-gate (DG) silicon-on-insulator (SOI) technology with planar independent self-aligned gates. The proposed sense amplifiers (SA) need 40% to 4 times less power, achieve a 10-15% increase in speed and have a 2.5 to 3.5 times larger tolerance to Vth and L mismatch compared to published DG SAs. Both architectures take advantage of the back gate in order to improve circuit properties. The new CSA is by 12% faster and reduces power consumption 3.3 times compared to the new VSA, with the latter having a significant advantage in size.

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