Implementation and Analysis of Low Power Reduction Techniques in Sense Amplifier

Abstract

In proposed work, low power reduction techniques such as footer stack, MTCMOS (Multi-Threshold CMOS), sleepy stack and sleepy keeper have been implemented in voltage-mode, current-mode and charge-transfer sense _amplifiers in customary gpdk 90nm technology documents using Cadence tool. Observations are mainly focused on power dissipation of different sense amplifier configurations. The simulation results show that the charge-transfer sense_amplifier consumes less power i. e 11.069 μW as compared to the power consumed by current sense and voltage sense amplifiers 54.245 μW and 86.66 μW respectively. Furthermore, proposed implementation of MTCMOS technique in current mode sense amplifier leads to a dramatical reduction i.e. 10-98% in power dissipation considering power supply voltage of 1.2V.