Abstract
Single Event Upsets (SEUs) represent a major challenge for digital electronics operated in a radiation environment. Triple Modular Redundancy (TMR) is one of the most popular approaches to increase digital electronics resilience to SEUs. Simulation is the most used approach for verifying the correct triplication of the designs. This contribution describes a novel approach for verifying the triplication. A formal verification tool is used, removing the need for a complete functional verification framework for the SEU injections in the design. The approach allows finding bugs earlier in the design phase hence reducing the development and debug time.
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