Fine-grain SEU mitigation for FPGAs using Partial TMR

Abstract

The mitigation of single-event upsets (SEUs) in field-programmable gate arrays (FPGAs) is an increasingly important subject as FPGAs are used in radiation environments such as space. Triple modular redundancy (TMR) is the most frequently used SEU mitigation technique but is very expensive in terms of area and power costs. These costs can be reduced by sacrificing some reliability and applying TMR to only part of the FPGA design. Our Partial TMR method focuses on the most critical sections of the design and increases reliability by applying TMR to continuous sections of the circuit. We introduce an automated software tool that uses the Partial TMR method to apply TMR incrementally until the specified percentage of resources are utilized. Thus the tool gives the maximum reliability gain for the specified area cost. The amount of mitigation applied can be chosen at a very fine level, giving the designer maximum flexibility when producing the final mitigated design.