Partitioning Triple Modular Redundancy for Single Event Upset Mitigation in FPGA

Abstract

The mitigation of single event upsets (SEUs) in field programmable gate arrays (FPGAs) is an increasingly important subject as both the static random access memory (SRAM) cells and the logic circuits in FPGAs are susceptible to SEUs. Among all SEU mitigation techniques, the triple modular redundancy (TMR) has become the most common practice because of its straightforward implementation and reliable results. The methodologies to perform partitioning TMR insertion to reduce SEUs in the FPGA logic paths are presented in this paper. It is proved that the maximal probability of two simultaneous errors decreases dramatically with the number of logic partitions in the TMR designs. It is reduced from 66.67% for minimum logic partition to 4.44% for maximum logic partition for the test circuit. The results presented in this paper suggest that there is a tradeoff between the number of logic partitions and combination property of TMR designs. For ground-based systems such as nuclear power plant (NPPs), where the overhead is insignificant, especially compared to reliability requirements, the maximum partition can be the best. While in space applications where area is at a premium, the optimal logic partition should be the medium partition.