The TMR Fault-Tolerant based on EHW Under Single Event Upset

Abstract

This chapter reflects fault tolerance in certain military applications, in atomic power plants, or on aircraft and introduces some ideas on how to apply evolution to existing fault tolerance schemes. Because of Field Programmable Gate Arrays (FPGAs) inherent time to-market, low NRE, and flexibility advantages over application-specific integrated circuits (ASICs) their popularity continues to grow in many applications, including space, military, and avionics. The extensive use of FPGAs in these applications underscores the importance of understanding the different effects on FPGAs of ionizing radiation components, such as neutrons, protons, and heavy ions. The chapter examines the cause and effects of Single Event Upset (SEU) and the SEU susceptibility. It also examines SEU mitigation techniques and discusses the susceptibility of static random access memories (SRAM) based FPGAs to SEUs. The chapter describes the ways of increasing the circuit's reliability with the help of evolutionary techniques, proposes the use of evolvable hardware (EHW) in the Triple Modular Redundancy (TMR) fault tolerant circuit design to achieve Evolutionary Fault Repair TMR fault-tolerance circuit, and illustrates the immunity of FPGA devices to SEU effects.