SEGR Analysis of Super Junction VDMOS using HfO2 as Gate Dielectric

Abstract

Single event gate rupture (SEGR) analysis was performed on a vertical double diffused metal oxide semiconductor field effect transistor (VDMOS) in which high energy charged particles were incidence at distinct locations typically normal to the device. The combination of SiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> -HfO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> as stack with an EOT of 110nm results in superior radiation hardening towards SEGR. By incorporating a super junction technique with high-k dielectric in the proposed device the increment in breakdown voltage (BV) was 270% and specific ON state resistance (RON SP) was lowered by 167% respectively. For simulation, an ion with a Linear Energy Transfer (LET) of 37.2MeV.cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /mg was used in Silvaco Atlas TCAD tool. Using these techniques high-k dielectric super junction VDMOS (HD SJ VDMOS) device can be used in direct current to direct current converters in satellites for space radiation environment.