Analysis of Single Event Gate Rupture in Trench Gate SJ-VDMOS with SiO2-Si3N4 Dielectric Stacking

Abstract

In this proposed work, single event gate rupture (SEGR) analysis was performed on a vertical double diffused metal oxide semiconductor field effect transistor (VDMOS) where the high-energy charged particles at different locations incident normally across the device. It was observed that with the combination of SiO2-Si3N4 (30nm, 130nm) stacking, the device shows better radiation hardening towards SEGR. The equivalent oxide thickness (EOT) of the dielectric layer is considered 100nm. Ions with different Linear Energy Transfer (LET) are investigated. Silvaco ATLAS TCAD tool was used. The above-proposed technique made the device Radhard and allows it to work in high-power applications in a radiation environment.