River routing and density minimization for channels with interchangeable terminals

Abstract

Programmable logic cells are widely used in VLSI design because of their structural regularity and flexibility. The terminals (or otherwise called pins) on these cells are interchangeable since their geometries are programmable. Terminals can be interchanged if they are on the same programmable cell. Moreover, the terminals of any logic gate can be inter changed without affecting the functionality of the given circuit. Our input instance is a channel routing problem with exit terminals. The logic cells on the channel sides have permutable terminals. The nets connect terminals on the cells and/or exit terminals. A methodology for performing the channel routing consists of (a) interchanging the terminals within each cell so that certain routing requirements (e.g., density, number of layers, etc.) are minimized, and (b) routing the new problem. We present a linear-time algorithm that detects whether there exists an interchange of the terminals that can lead to a river routable channel, and if so, we proceed with the interchange. Next, we turn our attention to the problem of finding interchanges that minimize the density of the channel. First we show that minimizing the channel density is NP-hard. For the restricted case of two terminal nets, however, we present a linear-time algorithm that finds an interchange that minimizes the density. Finally, we consider the special case where each multiterminal net has at most one terminal per cell. We present a linear-time algorithm that finds an interchange that minimizes the density of such problems. This is an important case since at gate level design each cell is a gate with permutable terminals.