A new algorithm with minimum track for four layer channel routing in VLSI design

Abstract

Channel routing is a key problem in VLSI physical design. The main goal of the channel routing problem is to reduce the area of an IC chip. If we concentrate on reducing track number in channel routing problem then automatically the area of an IC chip will be reduced. Here, we propose a new algorithm to reduce the number of tracks using four layers (two horizontal layers and two vertical layers). To be more specific, through this algorithm we convert a two-layer channel routing problem into a four-layer channel routing problem using HNCG and VCG of the channel. Next, we show the experimental results and graphical structure of that solution.