Via Minimization for Multi-layer Channel Routing in VLSI Design

Abstract

It is known that via minimization is a very important problem in multilayer channel routing. The main objective of via minimization is to improve the circuit performance and productivity, to reduce the completion rate of routing and also fabricate integrated circuit correctly. In this paper, we study on some important via minimization algorithms. Firstly we analyze via minimization problem in two-layer channel routing with movable terminals. In this assumption via minimization problem can be solve in polynomial time. Next we study a genetic algorithm for constrained via minimization. Next we observe how to minimize the number of vias using layout modification. The main significant of this method is to reduce the number of vias without increasing the routing area. Later we also study how via can be minimize in three layer channel routing. In this approach there is no any specific rule for layering and because of this result is better than earlier three layer channel routers. Lastly we analyze a heuristic algorithm to solve CVM problem for three layer channel routing. It is based on the breadth first search, there is no any restriction on layouts given as input and any wire segment can pass through without using via. Every heuristic algorithm constructs a graph model from a given layout. Lastly we have done one comparative study for all these algorithms and conclude this paper.