RF SOI CMOS technology on 1st and 2nd generation trap-rich high resistivity SOI wafers

Abstract

In this work three different types of UNIBOND™ Silicon-on-Insulator (SOI) wafers including one standard HR-SOI and two types of trap-rich high resistivity HR-SOI substrates named enhanced signal integrity high resistivity silicon-on-insulator (eSI HR-SOI) provided by SOITEC are studied and compared. The DC and RF performances of these wafers are compared by means of passive and active devices such as coplanar waveguide (CPW) lines, crosstalk- and noise injection-structures as well as partially-depleted (PD) SOI MOSFETs. It is demonstrated that by employing enhanced signal integrity high resistivity silicon-on-insulator (eSI HR-SOI) compared to HR-SOI wafer, a reduction of 24dB is measured on both generations of trap-rich HR-SOI for 2nd harmonics. Furthermore, it is shown that in eSI HR-SOI, digital substrate noise is effectively reduced compared with HR-SOI. Purely capacitive behavior of eSI HR-SOI is demonstrated by crosstalk structure. Reduction of self-heating effect in the trap-rich HR-SOI with thinner BOX is finally studied.