RF performance projections for 2D graphene transistors: Role of parasitics at the ballistic transport limit

Abstract

The modeled device structures are shown in Figure 1, (a) top-gated structure e ox = 20 and t ox = 1.5nm, and (b) back-gated structure with 90nm thick SiO 2 . The contact resistance and parasitic capacitance have also been taken into consideration in the simulations. Figure 2 shows the effect of M-G contacts on the transfer characteristics and transconductance, g m for the top-gated structure. The on-current, I on , can be increased with strong M-G coupling strength Δ or heavy contact induced doping (i.e. larger ΔE contact ). The off-current, I off , does not increase. Large ΔE contact increases g m , but the maximum g m does not show a strong dependence on Δ. We use Δ=50meV and ΔE contac = −0.4eV for rest of the simulations. Figure 3 shows the I DS vs. V GS and g m vs. V GS at different V DS for the top-gated structure. Large V DS yields a higher maximum g m , but low V DS shows better linearity with a broader ƒ T peak. Transfer characteristics with different channel lengths are shown in Figure 4. For the top-gated structure excellent gate electrostatics helps avoid short channel effects (SCE). I on remains the same for all channel lengths. I off increases about 1.5 times when L ch decreases from 100nm to 15nm due to direct source to drain tunneling. The rise in I off leads to g m degradation at L ch =15nm. In the back-gated structure, the on/off ratio is degraded at shorter channel lengths, and the minimum conduction point shifts. Figure 5 shows the effect of contact resistance on I D - V GS characteristics at L ch = 100nm. At V DS = 0.3V, compared with the intrinsic case, when R S/D = 0.5Ωmm, on/off ratio decreases 3x for the top-gated structure and 1.2x for the back-gated structure. I on reduces 22x for the top-gated structure and 6x for the back-gated structure. Figure 6 shows the comparison of ƒ T -V GS with different channel lengths at V DS = 0.3V. The cutoff frequency is calculated as ƒ T = 1/2πτ tot , where τ tot = L ch C gs /g m + C gd /g m + C gd (R S +R D ), C gs = ∂Q ch /∂V GS , R S/D = 0.5Ωmm, and C gd = 2pF/cm and 0.5pF/cm for the top-gated and the back-gated structures, respectively. Charging/discharging process is faster at shorter channel lengths, thus the peak ƒ T increases. In the back-gated structure, SCE is strong, thus the on/off ratio decreases and g m drops dramatically at short L ch . When L ch is shorter than 30nm, even the peak ƒ T drops. Figure 7 summarizes the ƒ T vs. L ch at V DS = 0.3V. The intrinsic ƒ T = <v>/2πL ch is added as a reference with the average ballistic velocity <v> = 2v F /π in 2D graphene. With R S/D = 0.5Ωmm and C gd = 2pF/cm, ƒ T drops 2x at L ch =100nm and 8x and L ch =15nm for the top-gated structure. For the back-gated structure, with R S/D = 0.5Ωmm and C gd = 0.5pF/cm, when L ch is below 70nm, ƒ T does not increase, and it even decreases when the channel length is below 30nm. Thus, parasitics currently dominate the performance, and major gains are expected with their reduction. This work is supported by the Semiconductor Research Corporation Nanoelectronics Research Initiative and the National Institute of Standards and Technology through the Midwest Institute for Nanoelectronics Discovery (MIND).