Review and Analysis of Variable Bit-precision MAC Microarchitectures for Energy-efficient AI Computation

Abstract

In this paper, we review and analyze the state-of-the-art bit-precision scalable multiply-accumulate (MAC) unit microarchitectures. To enable fast and energy-efficient neural network computation, many previous MAC microarchitectures have been explored, but it is hard to select an optimal approach because those works were usually evaluated in different experimental conditions. We first review various variable-bit MAC microarchitectures. Then, we synthesize the variable-bit hardware microarchitectures in a 28 nm technology, and we evaluate the synthesized designs using our custom architecture simulator. Using real benchmarks, we compare various bit-scalable hardware topologies to help researchers choose the most suitable microarchitecture for variable-bit hardware design.