Research of Underfill Delamination in Flip Chip by the J-Integral Method

Abstract

Fracture mechanics approaches have been used to study reliability problems in electronic packages, in particular, adhesion related failure in flip chip assembly. It was verified in this work that the J-integral with a special flat rectangular contour near the crack tip can be used as energy release rate at the interface between chip and underfill. Meanwhile, the delamination propagation rates at the interface was measured by using C-mode scanning acoustic microscope (C-SAM) inspection for two types of flip chip packages under thermal cycle loading. Finally, the half-empirical Paris equation, which can be used as a design base of delamination reliability in flip chip package, has been determined from the crack propagation rates measured and the energy release rates simulated.