Advanced Simulation/Modeling and Reliability of Fine Pitch (130um) Lead-Free Flip-Chip Package

Abstract

Flip-chip technology has been introduced in recent years which accommodate the ever increasing demands for higher performance and I/O density, while achieving smaller form factor and offering a cost effective solution. As the industry moves toward the 65nm and 45nm technology node, die sizes require a significant reduction while accommodating the need for tighter and finer pitches. For decades, the C4 process has served as the main interconnect method in the flip-chip package. But with bump pitches shrinking, the solder bump based C4 process is facing challenges in terms of reducing pitch and underfill process. At the same time, increasing challenges for flip-chip are seen by the movement toward lead-free solder bumps and low-k dielectric layers. This work conducted simulations and analyses on Tessera developmental μPILR flip chip package incorporating a 130um pitch bump array, using 3-D finite element method (FEM). This study explores the effect of various design parameters on package reliability while providing suggestions for selecting packaging materials. Based on modeling data certain set of over mold, underfill and thermal interface materials enhance overall package reliability performance. Solder fatigue life prediction was performed and solder bump reliability was compared for Tessera flip chip technology and standard flip chip solder joints using Modified Anand solder material properties and Darveaux fatigue life prediction theory. Further more, fracture mechanics approach was applied, and energy release rates were obtained in order to check reliability of low-k dielectric layer, provided passive/low-k material selection. The data presented here provides a baseline for reliability/feasibility of Tessera developmental μPILR flip chip package design for 130um bump pitch. Experimental reliability data is not complete at this time but will be available and published soon.