Research and design of reconfigurable composite field multiplication in symmetric cipher algorithms

Abstract

The composite field multiplication is an important and complex module in symmetric cipher algorithms, and its realization performance directly restricts the processing speed of symmetric cipher algorithms. Based on the characteristics of composite field multiplication in symmetric cipher algorithms and the realization principle of its reconfigurable architectures, this paper describes the reconfigurable composite field multiplication over GF((28) k ) (k=1,2,3,4) in RISC (reduced instruction set computer) processor and VLIW (very long instruction word) processor architecture, respectively. Through configuration, the architectures can realize the composite field multiplication over GF (28), GF ((28)2), GF ((28)3) and GF ((28)4) flexibly and efficiently. We simulated the function of circuits and synthesized the reconfigurable design based on the 0.18µm CMOS (complementary metal oxide semiconductor) standard cell library and the comparison with other same kind designs. The result shows that the reconfigurable design proposed in the paper can provide higher efficiency under the premise of flexibility.