Design and implementation of VLIW DSP processors for high ended embedded based systems

Abstract

Development of high performance embedded platforms concentrates on handling huge computational requirements of complex algorithm. For high ended applications, execution of the processor will shift agreeing to the code being executed. Consequent enlightening can be depending on past instruction for the execution. Due to high dynamic energy and long latency on write operations, Reduced Instruction Set Computing (RISC) processors cannot be employed for executing some applications as it execute more instructions at a time. Its other limitations are requirement of large memory cache and hardware complexity. Due to this, designing a compiler using RISC is complicated. Due to all these issues, conventional RISC processor plan endures from less performance. One of the techniques that can be used to boost the processing in such systems is the Instruction Level Parallelism (ILP). The VLIW architecture uses Very Long Instruction Word (VLIW) architecture. This architecture is one of the promising alternative work which provides a great capabilities within an energy budget. Low power consumption and less hardware complexity are some of the advantages of VLIW processor when compared to RISC processor. However, the overall power consumption taken by the register file of this VLIW architecture is very critical. Result from the centralized resources and global communication implies that the traditional VLIW design do not scale efficiently due to the bottlenecks problem. In this paper, a design of processor to scale down the leakage energy of the register files. The proposed work also minimizes the overhead of the added hardware without performance degradation and resolves the issue conflicts among multiple threads.