Abstract
A novel concept of logic redundancy insertion is presented that facilitates significant latency reduction in self‐timed adder circuits. The proposed concept is universal in the sense that it can be extended to a variety of self‐timed design methods. Redundant logic can be incorporated to generate efficient self‐timed realizations of iterative logic specifications. Based on the case study of a 32‐bit self‐timed carry‐ripple adder, it has been found that redundant implementations minimize the data path latency by 21.1% at the expense of increases in area and power by 2.3% and 0.8% on average compared to their nonredundant counterparts. However, when considering further peephole logic optimizations, it has been observed in a specific scenario that the delay reduction could be as high as 31% while accompanied by only meager area and power penalties of 0.6% and 1.2%, respectively. Moreover, redundant logic adders pave the way for spacer propagation in constant time and garner actual case latency for addition of valid data.
Highlights
The 2009 International Technology Roadmap on Semiconductor (ITRS) design predicts that adaptive digital circuits will be increasingly necessary for the future as a consequence of increase in variability [1]
To demonstrate the usefulness of the proposed concept of logic redundancy insertion, simulations have been performed by considering a 32-bit self-timed ripple carry adder (RCA) architecture
Since identical registers and a similar completion detection circuit were used for all the 32bit adders, the area and power metrics can be correlated with that of the function block, paving the way for a straightforward comparison between adders synthesized on the basis of different self-timed design methods
Summary
The 2009 International Technology Roadmap on Semiconductor (ITRS) design predicts that adaptive digital circuits will be increasingly necessary for the future as a consequence of increase in variability [1]. Two binary bits of information are represented by asserting only half of the physical lines as logic “high” in the 1-of-4 code in comparison with a dual-rail code, both the coding schemes require the same number of physical lines. Higher order encoding schemes are available, apart from the dual-rail code that allows easier mapping between conventional binary functions, the other widely used DI code is the 1-of-4 code This is owing to the reason that for self-timed data paths, encoding by sender and membership test and decoding by receiver are important aspects, and the encoding and decoding complexity is dependent on the message space to be coded [19]. The signaling scheme for strong- and weak-indication timing regimes in terms of the input-output characteristics is illustrated graphically, which summarizes the sequencing constraints mentioned above. In general for iterative circuits, weakly indicating implementations are preferable compared to strongly indicating versions since the former’s computation time is data dependent for valid data and may exhibit constant latency for spacer data, while the latter is always bound by worst-case latency for both valid data and spacers [21]
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