Built In Self Repair Architecture for SRAM Using Redundancy Logic

Abstract

With scaling of device dimensions in nanometer technologies, a large number of cells in memory array are expected to be faulty due to process parameter variations. Hence this paper analyzes SRAM (Static Random Access Memory) cell failure, by mapping them to fault models and proposes a new BISR (Built In Self Repair) architecture for SRAM, suitable for high performance application. Proposed BISR design is composed of a BIST (Built In Self Test) module and BIRA (Built In Redundancy Analysis) module. March tests are used in BIST to test memory chips. Faulty addresses are stored in the redundancy logic. The BIRA module executes an efficient redundancy analysis algorithm proposed for SRAM based on spare rows. The process of detecting the faulty line and redirecting to the next available word line are done during the reset period. Hence the power consumption and the area penalty are kept minimum. The BISR concept is described in RTL code. The redundancy and BIST logic is fully synthesizable and can be reused.