Modeling of redundancy analyzer in BISR for RAM

Abstract

In the current SoC implementation embedded memories are most widely used cores. They usually occupy a significant portion of the chip area, and dominate the manufacturing yield of the chip. Embedded memories have become very vulnerable to even minor process variations, resulting in low manufacturing yield & reliability. Efficient yield-enhancement techniques for embedded memories are thus important for SoC. The Built in Self Repair (BISR) includes two modules Built in Self Test (BIST) and Built-In Redundancy Analysis (BIRA). The BIRA circuit performs the redundancy allocation using the proposed RA algorithm. The purpose of RA is to allocate appropriate redundant (spare) memory elements to replace the defective cells, such that the utilization of the spare elements can be optimized. In a memory with BISR, the RA collects the fault information from the BIST. RA performs the analysis after the fault bit-map of a defective memory is constructed. In this paper, it is proposed to model a RA technique for a 2D Random Access Memory of 512 bit with spare rows and columns. This Analyzer decides which spare element to be allocated for a fault adaptively by considering the fault count on each row/column. The model is simulated using Aldec Active HDL version 6.3 and synthesised using Xilinx ISE tool 9.1.