Reduction method of gate-to-drain capacitance by oxide spacer formation in tunnel field-effect transistor with elevated drain

Abstract

A novel fabrication method is proposed to reduce large gate-to-drain capacitance (CGD) and to improve AC switching characteristics in tunnel field-effect transistor (TFETs) with elevated drain (TFETED). In the proposed method, gate oxide at drain region (GDOX) is selectively formed through oxide deposition and spacer-etch process. Furthermore, the thicknesses of the GDOX are simply controlled by the amount of the oxide deposition and etch. Mixed-mode device and circuit technology computer aided design (TCAD) simulations are performed to verify the effects of the GDOX thickness on DC and AC switching characteristics of a TFETED inverter. As a result, it is found that AC switching characteristics such as output voltage pre-shoot and falling/rising delay are improved with nearly unchanged DC characteristics by thicker GDOX. This improvement is explained successfully by reduced CGD and positive shifted gate voltage (VG) versus CGD curves with the thicker GDOX.