Controlling the ambipolar current in ultrathin SOI tunnel FETs using the back-bias effect

Abstract

A two-dimensional (2-D) technology computer-aided design (TCAD)-based simulation study of the back bias in the ultrathin silicon-on-insulator (SOI) tunnel field-effect transistor (TFET) is presented. The transfer characteristics of a conventional TFET called the back-bias TFET (BB-TFET) depend on the back bias and the oxide thickness below the TFET epitaxial layer. The back bias affects the electric field at the source/channel and drain/channel junctions, hence both the ON-state current ($$I_{\mathrm{ON}}$$) and the ambipolar current ($$I_{\mathrm{AMB}}$$) reduce with a negative back-bias voltage. This reduction in $$I_{\mathrm{ON}}$$ is not desirable in a TFET, hence a modified TFET structure called the back-bias underdrain TFET (BBUD-TFET) is proposed. In the BBUD-TFET, the back bias is applied on a p-Si pocket placed under the drain region, which is isolated using an ultrathin oxide. The back bias in the proposed BBUD-TFET mainly affects the electric field at the drain/channel interface, having a negligible impact on the source/channel interface. The BBUD-TFET structure is analyzed with $${\mathrm{SiO}}_2$$ or $${\mathrm{HfO}}_2$$ as the gate oxide. In the BBUD-TFET with $${\mathrm{HfO}}_2$$ as the gate oxide, the back bias completely suppresses the ambipolar current without reducing $$I_{\mathrm{ON}}$$. Furthermore, the oxide thickness and back-bias voltage are optimized for the BBUD-TFET structure. In this study, 2-D TCAD simulations are carried out to investigate and analyze the performance of the BB-TFET and BBUD-TFET.