Reduced delay sensitivity to process induced variability in current sensing interconnects

Abstract

The effect of process induced variability in long global on-chip interconnects caused by critical dimension control and intrinsic fluctuation of transistor threshold voltage is analysed for current and voltage mode signalling. Projections in scaled CMOS technologies show that current sensing interconnects exhibit smaller mean delay and sensitivity to parameter fluctuations. The standard deviation of delay exhibits an increasing dependency on process variations at the low and high extremes of receiver to driver circuit resistance ratios. An experimental on-chip bus demonstrates the reduced delay variability in current sensing schemes.