High-performance Current Mode Receiver Design for On-chip VLSI Interconnects

Abstract

This paper presents an efficient receiver design for on-chip current mode signaling (CMS) interconnects. The CMS interconnects using proposed receiver have 34 % lesser delay for interconnect length of 20 mm and around 3 times higher throughput at room temperature than that of conventional voltage mode signaling (VMS) interconnects. The analysis is performed for single-ended interconnects. The present work is useful for analyzing the effectiveness of voltage and current mode signaling techniques for on-chip interconnects. The simulations are performed for 180-nm technology node using Tanner EDA tool.