Abstract
Digital systems built based on field-programmable-gate-arrays (FPGAs) are increasingly being used in safety-critical computer systems. These systems typically require high levels of integrity, reliability, and performance to ensure the correct operation of the critical application in which the digital systems are embedded. To achieve the safety and functional objectives, many hardware architectural scenarios based on fault tolerance techniques were proposed. This research paper presents a new dependable digital system (DDS) that consists of fault tolerant blocks (FTBs), spare functional blocks (SFBs), synchronization units, and input output units. Markov-based chain have been used to model the correct operation of the proposed hardware system that is targeted to be realized on FPGA-based technology. This system was designed to be reliable against transient faults (TF), permanent faults (PF), and hardware common cause failures (CCF). The reliability analysis of the proposed system was accomplished with Markov modeling techniques which could express the regenerative behavior of the digital system. Certain states in the system represent system failure, while others represent fault-free behavior in the presence of faults. Finally, based on the MathWorks Simulink simulation results of modeling the DDS digital system, the system does meet its functionality and reliability requirements.
Published Version
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