Pseudo-random testing of CMOS ternary logic circuits

C. Rozon,H.T. Mouftah

doi:10.1109/ismvl.1988.5189

Pseudo-random testing of CMOS ternary logic circuits

C. Rozon, H.T. Mouftah

https://doi.org/10.1109/ismvl.1988.5189

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Publication Date: Jan 1, 1988

Citations: 2

Affiliation: Royal Military College of Canada, Queen's University

#Built-in Logic Block Observer #Logic Block Observer + Show 8 more

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Abstract

Two structures that can be used to test ternary logic VLSI circuits are described and compared: the ternary BILBO (built-in logic block observer) and the ternary CALBO (cellular automaton logic block observer). These structures can be used to generate pseudorandom test patterns and signatures. Fault coverage and aliasing are also obtained and compared when each structure is used to test a four-trit ternary arithmetic logic unit. BILBO and CALBO can be used advantageously to test binary VLSI systems as well. >

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