Cellular Automata Logic Block Observer Based Testing for Network-on-Chip Architecture

Abstract

Necessity to test the logic circuits has increased rapidly due to the increase in number of applications being hosted on a single chip. This in turn has demanded the design of testing architectures which are capable of providing high fault coverage with less resource utilization and minimal power usage. Cellular Automata Logic Block Observer (CALBO), a technique homologous to Built-In Logic Block Observer (BILBO), has been considered in this paper to test the routers which are considered as important components of a Network-on-Chip (NoC) architecture. The resource utilization and power report of the design have been successfully generated to list out the advantages of the CALBO in comparison to BILBO for the architecture considered.