Abstract

Reversible logic is gaining more importance day by day, because of its feature of low power dissipation which is the basic need in designing nano electronic devices, bioinformatics, low power CMOS designs and quantum computing. Reversible logic is one which realizes n-input n-output functions that map each possible input vector to a unique output vector. It is a promising computer design paradigm for constructing arithmetic and logic units which are the basic building blocks of computer that do not dissipate heat. After designing a system, it is also equal important to test it. In this paper reversible ALU (Arithmetic and Logical Unit) performing four operations (Addition, Multiplication, Subtraction and Bit wise- AND) is implemented and the simulated results like power consumed, delay and area obtained are compared with that of conventional ALU. Testing is also done on proposed reversible ALU by using BILBO (Built—in Logic Block Observer) blocks, which was the first BIST (Built-in Self Test) architecture to be proposed and undergo wide spread use. The proposed reversible ALU is implemented and simulated using Verilog HDL in Xilinx 13.4 version.

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call

Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.