Proposal of a partial-ground-plane (PGP) silicon-on-insulator (SOI) MOSFET for deep sub-0.1-μm channel regime

Abstract

This letter proposes a new device structure which is called the partial-ground-plane (PGP) silicon-on-insulator (SOI) MOSFET. The PGP SOI MOSFET minimizes the short-channel effect (SCE) compared to the conventional single-gate (SG) SOI MOSFET because the gate-induced field in the SOI layer is held high by the PGP region. This results in a lower stand-by leakage current. The PGP SOI MOSFET also shows much better switching performance and extremely high analog performance because of its smaller parasitic capacitance compared to the conventional ground-plane (GP) device. Thus, it is shown that the PGP SOI MOSFET is a promising candidate for future deep-sub-0.1-/spl mu/m mixed-mode LSIs.