Abstract
Heterogeneous integration stands as a pivotal strategy in the semiconductor technology realm. As process nodes relentlessly scale down from 16nm to 5nm and beyond, CMOS component speeds soar. This dynamic corresponds to incorporating twice the component count within the same space every 18-24 months. The evolution from CoS (Chip on Substrate) to CoW (Chip on Wafer) marks a significant advancement. CoW integrates chips onto an interposer, applies wafer-level molding, and culminates with a flip chip (FC) substrate connection. This technology offers a superior physical structure to accommodate extensive die and larger interposer dimensions. The technical paper titled ‘Defluxing of Copper Pillar Bumped Flip Chips,’ initially presented at IPC Apex 2022 and subsequently at IMAPS Device Packaging Conference 2023, discussed a comparative study. The study confirmed that the De-ionized water inline cleaning system faces consistent and effective cleaning challenges beneath low standoff components under copper pillar packages featuring 150μm pitch and a 30μm Cu pillar height when compared to low concentration alkaline cleaning agents. This follow-up study is a continuation of the initial effort, focusing on cleaning under next tier of ultra-fine pitch CoW devices with bump pitches under 25μm and bump counts surpassing 150K. The author adhered to the same low-concentration alkaline cleaning agent for testing, exploring the impact of wash temperatures and conveyor belt speed. The assessment employed analytical/functional tests, including Visual Inspection, FTIR with color mapping, and SEM/EDX analysis.
Published Version
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