Generational changes of flip chip interconnection technology

Abstract

Flip chip (FC) assembly technology was developed by IBM in 1960s and widely used in high functional performances of electronic devices in computer, military, mobile, automobile etc. The use of solder bumps to make electrical connection between the substrate and chip can provide shorter path and reduce latency issues as compared to wire bonding. Additionally, flip chip is an area array bonding, which allows high I/O (Input/Output) density within a single die, and thus driving the semiconductor scaling process. Over the decades, the number of interconnection within flip chip devices has been increased from hundreds to half million bump joints. For the purpose to achieving the massive high I/O counts, the miniature of bump size and bump pitch plays a significant role, and also face technology challenges. Chip interconnection bumps technology has been evolved over fifty years. Generally, it could be divided into three generations in according to the connection method. The first generation typically has the bump pitch over 130μm, while the second generation's bump pitch is within a range from 40 to 130 μm. And the most recent one (the third generation) has been developed to be smaller than 30μm. Each generation has unique bonding technology and encapsulation materials to make different assembly packages and form factors. For the bump pitch over 130μm, which is normally composed of solder ball, is so called controller collapse chip connect (C4) bumps. The bumps in the device, up to nearly thousand counts, are usually bonded on to ceramic or organic substrate using flip chip bonder with fluxing and reflow soldering processes. Further, flux cleaning is introduced to remove flux residue, which is followed by the underfill or mold encapsulation process to protect the solder connections. Flip Chip Ball Grid Array (FCBGA) and Flip Chip Chip Scale Package (FCCSP) are the classic two package types of this C4 joint generation. As for the interconnection technology with bump pitch between 40 to 130μm, which is so-called micro bump or chip connection (C2) bumps, the thermal-mechanical warpage and bonding precision are the major challenges. The copper pillar with thinner solder tip is generally produced to meet the finer pitch requirements. However, the collapsing process during soldering is hard to compensate the warpage induced by CTE-mismatch between chips and substrates, which drives the implementation of through silicon interposer (TSI) to be a solution for the thermal mismatch concern. Additionally, thermal-compression bonding (TCB) technology are high precision bonder are essential requirements for die bonding process. Owing to the miniaturization of bump scaling, the flux cleaning process is getting hard to achieve fully cleaned inside the package. Thus, the demand for fluxless or non-clean flux are getting popular. Furthermore, the new encapsulated materials like non-conduction paste (NCP) or non-conductive film (NCF) are now being applied to enable the fine-pitch assembly and the 2.5D packages. The 3DIC assembly, the most advanced package type, is moving forward to design the bump pitch to 30μm and below. The existing soldering process can no longer support this new bump scaling and high precision requirement due to the physical limitation of solder tip. So the processes such as direct Cu-to-Cu (Copper-to-Copper) bonding using thermal diffusion process under ultra-high vacuum environments and the electroless plating are getting more attention in recent years. The studies on Cu-to-Cu interconnection for ultra-fine pitch bonding are still in exploration stage and already showing some positive results. The particle control for finer pitch and smaller interconnection size will become a major consideration factor for yield. In view of flip chip technology evolution, this paper is going to discuss the requirements of these interconnections in term of materials, machines, environments, and processes. Further, the changing of bump interconnection in flip chip package will be discussed as well.