Power Envelope Analyses of Chiplet Module and System-on-Chip

Abstract

A novel power management method was developed to predict the reliability of silicon, and the method is applicable to both multichip and System-on-Chip packages. The System-on-Chip here refers to a single die which has many functional blocks and each functional block can be treated as an individual die. With power envelope analysis, the risk values of die powers are determined. An effective risk value considerig all the powers of dies may be defined to determine the overall impact. As circuit design engineers select and define the power magnitudes of dies, the distances to the threshold planes on the power envelope plots are calculated to determine the thermal reliability. The method also allows reliability engineers to define a weight scale value to reflect the ruling of each die, and this is very impportant for practical design and assembly because different dies may have different levels of reliability concerns. An advanced histogram method was used to compare the impact of power magnitudes of dies on the thermal reliability. We have implemented the approach to study the thermal reliability of a chiplet module and a System-on-Chip. In conclusion, this paper implements a power envelope analysis to help determine the allowed and optimized powers of the dies on a chiplet module or the powers of the functional blocks on an SoC package.