Abstract
We propose a logic synthesis system that includes power optimization after technology mapping. Our approach is unique in that our post-mapping logic transformations take into account information on circuit delay, capacitance, arrival times, glitches, etc., to provide much better accuracy than previously proposed technology-independent power optimization methods. By changing connections in a mapped circuit, we achieve power improvements up to 13% in case of area- or delay-optimized circuits, with reductions also in area and delay. We show that by applying the proposed technique on circuits that are already restructured for lower switching activity using the technique presented in [11], total power savings up to 59% in case of area-optimized circuits and 38% in case of delay-optimized circuits are achievable. The post-mapping transformations are based on the transition density model of circuit switching activity and the concept of permissible logic functions. The techniques presented here are applicable equally well to both synchronous and asynchronous circuits. The power measurements are done under a general delay model.
Highlights
The high device count and clock frequency of modern ICs has made power dissipation of VLSI chips a major consideration during chip design
While it is important to attack the synthesis problem at all levels, in this paper we focus on the logic synthesis phase and propose a new algorithm for optimization in a post-technology mapping step that achieves lower power circuits on a variety of test cases
While reduction of power supply voltage and power-down strategies are already common in industry, additional power reduction can be obtained at the logic optimization and technology-binding phases of logic synthesis
Summary
The high device count and clock frequency of modern ICs has made power dissipation of VLSI chips a major consideration during chip design. The power-dissipation depends on the switching activity inside the circuit, which in turn depends on the input switching pattern and the speci c implementation of the circuit This complicates the low-power synthesis problem, since i exact input signals may not be known during the design phase and ii the traditional synthesis techniques of optimizing a technology independent circuit model become inadequate. In order to automatically nd a low-power implementation of a circuit design, we propose a new power-reducing logic transformation to be applied after the technology-mapping stage of logic synthesis. This transformation is proposed to augment any power optimization e ort that is carried out at the technologyindependent phases of logic synthesis.
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