A high-speed and low-power synchronous and asynchronous packaging circuit based on standard gates under four-phase one-hot encoding

Abstract

Compared with common bus system, GALS (Global Asynchronous Locally Synchronous) bus system can combine the respective advantages of synchronous circuits and asynchronous circuits, and is trend of System-on-Chip design. However, different data encodings are applied in synchronous circuits and asynchronous circuits, which makes it impossible to achieve the cooperation of synchronous modules and asynchronous modules, thus synchronous and asynchronous packaging circuits become the research focus in GALS(globally asynchronous locally synchronous) bus systems. In this paper, a synchronous and asynchronous packaging circuit under four-phase one-hot encoding is designed based on the standard gates. Verifications of the packaging circuit are implemented on Xilinx Viretex5 of 65nm CMOS technology. The results show that the power is reduced by 58.3%, the working speed of synchronous-to-asynchronous module increased by 54.6%, and the working speed of asynchronous-to-synchronous module increased by 64.7% compared with the traditional suspended clock packaging circuits.