Abstract
A new high speed high density poly I 2L structure with deposited polysilicon collector is analyzed and modeled. The switching speed of the proposed poly I 2L structure is 4 times higher than that of the conventional structures and the packing density is improved by a factor of 2. The proposed poly I 2L structure is gnvestigated using a developed computer simulation model. Parameters sensitivity analysis of the structure is given. The minimum gate delay decreases as the intrinsic base sheet resistivity is increased and as the thin epitaxial layer under the base is decreased. Down scaling effects are discussed. It is shown that a lateral shift of PDP curves along the current axis is proportional to the change in the device area and the IR drop in npn base is proportional to the scaling factor. A structure with technology linewidth L = 2.5 μm exhibits minimum gate delay of 0.6 ns at 150 μA for fan-out F = 3, and a power-delay product of 30 fJ at low current levels. Simulation results are compared with experimental measurements performed on a given poly I 2L structure and good agreement has been observed.
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