System Level IR Drop Impact on Chip Power Performance Signoff for RISC-V System on Chip

Abstract

Understanding of how a chip power performance is impacted by the IR drop of a power delivery network (PDN) enables system operating conditions to be optimized. It allows IR drop impacts to a silicon chip to be identified and fixed early during design phases. Conventionally, the static and dynamic IR drop analysis for a silicon chip only considers the impact of silicon level power switching gates and metal routing. Such an analysis approach assumes the power supply from voltage regulator module (VRM) to silicon bumps is noise-free and steady, without taking the impacts of system level components into considerations [1]–[4]. In our opinions, such an analysis approach is unduly optimistic and causes IR drop signoff to be less reliable. This paper uses a RISC-V CPU as a case study to illustrate the importance of the external components in an IR drop analysis. The characterization results show that an IR drop of 100mV caused by PDN impedance can result in the targeted clock speed to be reduced by up to 500MHz, which is equivalent to a 50% performance degradation for a 1GHz CPU and is significant. Then, the impact of system level IR drop caused by package, board and VRM to a silicon chip power performance is further shown. A comparison between the conventional Redhawk chip IR drop simulation and our approach is presented. Our modelling methodology, which uses a system-level distributed PDN to increase IR drop analysis accuracy has also been described in detail. It is shown that external factors including package, board and VRM can induce up to 5.8% additional IR drop, or, 0. 058V for a 1V power supply. This may cause the targeted clock speed to be reduced by up to 250MHz in the actual silicon. It is demonstrated that the intrinsic resistance and impedance of PDN if not being managed properly could negate the power delivery efficiency and impacting silicon performance.