A general technique for designing totally self-checking checker for 1-out-of-N code with minimum gate delay

Abstract

An efficient technique for designing a totally self-checking checker for 1/n code (n>3) with minimum possible gate delay is proposed. The checker consists of a 1/n to k/2k translator and a k/2k code checker. The translator is implemented using a NOR array and checker using a NOR-NOR PLA. The design technique is applicable for all but a few values of n. It has been shown that the checkers constructed using the proposed technique occupy minimum or near-minimum chip area depending on the value of n. This new technique also has the advantage over existing ones in terms of speed or hardware.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>