Design a 24-bits pipeline phase accumulator for direct digital frequency synthesizer

Abstract

This paper present a novel design of high speed phase accumulator for direct digital frequency synthesizer by connecting blocks of the carry-lookahead adder in each pipeline stage, the carries ripple between the stages. The proposed 24-bits PA consist of three pipeline stages with 8-bits per stage, and exploits the advantage of carry-lookahead adder to get the carry out of many input bits at the end of final stage, directly with minimum gate delay, As such, this process can reduce the time gate delay. Comparing results between similar phase accumulator designs with ripple carry adder, using the ALTERA software (Quartus II) reveals that the phase accumulator designs with carry-lookahead adder run faster than phase accumulator with ripple carry adder in approximately 22%.