PMLS — A parallel multi-level VLSI simulator

Abstract

Simulation is a key element in modern and future digital circuit design. However, simulation becomes a bottleneck with increasing design complexity. There are mainly two ways to get out of this situation: reduction of the simulation load through multi-level simulation and acceleration of the simulation through exploitation of parallelism. This paper reports of a new Parallel Multi-level VLSI Simulator (PMLS) for a general purpose parallel machine which combines multi-leveling and exploitation of parallelism at the circuit level. The VLSI simulator is implemented in the object-oriented language POOL and runs on the parallel DOOM machine. The paper surveys briefly the principles of digital-circuit simulation, the possibilities of exploiting parallelism, the DOOM machine, its programming language POOL, and describes the design and implementation of the simulator. Preliminary performance figures are also given.