Abstract
Simulation is a key element in modern and future digital circuit design. However, simulation becomes a bottleneck with increasing design complexity. There are mainly two ways to get out of this situation: reduction of the simulation load through multi-level simulation and acceleration of the simulation through exploitation of parallelism.This paper deals with the development of a VLSI-Simulator which combines both approaches to achieve optimal performance. It is an informal overview of the work of AEG and its subcontractor Technische Universität Berlin carried out within ESPRIT Project 415.KeywordsParallel ProcessingDigital CircuitFault SimulationAlgorithm LevelGate LevelThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.
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