Multi-level VLSI simulator for general purpose parallel machines

Abstract

The paper reports of a new Parallel Multi-Level VLSI Simulator (PMLS) for general purpose message-passing parallel machines which combines multi-leveling and exploitation of parallelism at the circuit level. The VLSI simulator is implemented in the object-oriented language POOL and runs on the parallel DOOM machine. Implementations on iPSC/2 and on a Transputer-Network are in progress. The paper surveys briefly the principles of digital-circuit simulation, the possibilities of exploiting parallelism, and describes the design and implementation of the simulator. Performance figures are also given. >