Partitioning strategies within a distributed multilevel logic simulator including dynamic repartitioning

Abstract

Standard gate and switch level simulators are not capable of simulating accurate behavior of certain properties of BiCMOS digital circuits such as bidirectionality and charge sharing. Therefore, the parallelizing and mixing of timing level simulation and gate level simulation within a multilevel simulator would provide an effective balance between simulation speed and functional accuracy. The ability of the simulation system to change its internal partitioning during simulation time is presented. This feature is called dynamic repartitioning and improves the speedup of parallel logic simulation about 20-40% using small numbers of subsimulators. >