Physical insights of interface traps and self-heating effect on electrical response of DMG FinFETs in overlap and underlap configurations: analog/RF perspective

Abstract

This paper presents a thorough analysis on analog/RF parameters including interface trap charges (ITCs) of two different densities of states (DOS) along with self-heating on the performance of DMG FinFETs in Overlap and Underlap configurations. Initially, the independent simulations for acceptor ITCs and Self-heating in conventional device reveals that performance degradation caused by Self-heating is more prominent (25.03%) than uniform acceptor ITCs (9.46%). In consecutive step, the cumulative impact of both acceptor ITCs and Self-heating on DC and RF/analog parameters are carried out. Investigation reveals that as the impact of self-heating is larger in overlap configuration, the degradation in drain current is higher in overlap configuration (45.2%, 54.5%) as compared to conventional (30.4%, 40.96%) and underlap (37.2%, 52.8%) configurations for both Uniform and Gaussian trap distributions, respectively.